Crossbar structure with mechanism for generating constant outputs

ABSTRACT

Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed.

TECHNICAL FIELD

Embodiments relate to the field of integrated circuits; In particular tocrossbar devices and their use in reconfigurable circuits.

BACKGROUND

Crossbar devices for programmatically connecting n inputs to m outputsare known in the art. U.S. Pat. No. 6,874,136 describes a crossbardevice, and reconfigurable circuits having such a crossbar device. Invarious embodiments, the crossbar device includes pluralities of chainsof pass transistors to selectively couple the input lines to the outputlines. Memory elements and decoder logic facilitate the selectivecoupling. In such a crossbar structure, each of n inputs can beconnected to any m outputs, but each of the m outputs can be connectedto only one input. Reconfigurable circuits can use such a crossbarcircuit to arbitrarily connect fixed and/or programmable logicstructures together depending on the desired functionality.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be readily understood by the following detaileddescription in conjunction with the accompanying drawings. Embodimentsare illustrated by way of example and not by way of limitation in thefigures of the accompanying drawings.

FIG. 1 illustrates a crossbar structure having a mechanism forgenerating constant outputs in accordance with various embodiments;

FIG. 2 illustrates a crossbar structure having a mechanism forgenerating a constant ground-level voltage according to embodiments;

FIG. 3 illustrates a crossbar structure having a mechanism to generateconstant outputs and with an additional pass transistor used to selectbetween groups of inputs in accordance with various embodiments;

FIG. 4 illustrates a crossbar structure having a mechanism to generateconstant outputs and with a structure to make some inputs operate fasterin accordance with various embodiments; and

FIG. 5 illustrates a crossbar structure to minimize the skew betweeninputs and the output in accordance with various embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which are shownby way of illustration embodiments in which the invention may bepracticed. It is to be understood that other embodiments may be utilizedand structural or logical changes may be made without departing from thescope of the disclosure. Therefore, the following detailed descriptionis not to be taken in a limiting sense, and the scope of embodiments isdefined by the appended claims and their equivalents.

Various operations may be described as multiple discrete operations inturn, in a manner that may be helpful in understanding embodiments;however, the order of description should not be construed to imply thatthese operations are order dependent. Also, embodiments may have feweroperations than described. A description of multiple discrete operationsshould not be construed to imply that all operations are necessary.Also, embodiments may have fewer operations than described. Adescription of multiple discrete operations should not be construed toimply that all operations are necessary.

The description may use perspective-based descriptions such as up/down,back/front, and top/bottom. Such descriptions are merely used tofacilitate the discussion and are not intended to restrict theapplication of embodiments.

The terms “coupled” and “connected,” along with their derivatives, maybe used. It should be understood that these terms are not intended assynonyms for each other. Rather, in particular embodiments, “connected”may be used to indicate that two or more elements are in direct physicalor electrical contact with each other. “Coupled” may mean that two ormore elements are in direct physical or electrical contact. However,“coupled” may also mean that two or more elements are not in directcontact with each other, but yet still cooperate or interact with eachother.

For the purposes of the description, a phrase in the form “A/B” means Aor B. For the purposes of the description, a phrase in the form “Aand/or B” means “(A), (B), or (A and B)”. For the purposes of thedescription, a phrase in the form “at least one of A, B, and C” means“(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C)”. Forthe purposes of the description, a phrase in the form “(A)B” means “(B)or (AB)” that is, A is an optional element.

The description may use the phrases “in an embodiment,” or “inembodiments,” which may each refer to one or more of the same ordifferent embodiments. Furthermore, the terms “comprising,” “including,”“having,” and the like, as used with respect to embodiments, aresynonymous.

A crossbar structure according to embodiments may include a mechanism toprovide constant output (typically a voltage representing either a logic“1” or “0”) when no inputs are selected to be connected to a crossbaroutput. This may provide an ability to disconnect all inputs from theinternal capacitance of the crossbar device as well as provide aconstant value as an input to logic functions without taking upcomputational or routing resources. Control signals that may be used toselect the input to be connected to an output may also be used toselectively enable a special chain of transistors, or other componenttypes, connected to the output. This special chain of transistors mayalso be coupled to a voltage source. When all control signals are set toselectively disable all inputs from the output, each transistor in thespecial chain of transistors connected to the voltage source may beselectively enabled. This in turn may drive the output to a constantvoltage in embodiments.

Crossbar structures according to embodiments may be provided inconfigurable and/or reconfigurable circuits. Such reconfigurablecircuits may be used to program a particular application. Suchapplications may require constant logic values be provided to logicelements of the reconfigurable circuit. In prior art reconfigurablecircuits, providing such constant values requires utilizingcomputational resources. Embodiments therefore may free up computationalresources to perform other useful computational functions besidesproviding a constant-level voltage or signal.

FIG. 1 illustrates a crossbar structure having a mechanism forgenerating constant outputs in accordance with various embodiments.Crossbar structure 100 may include a plurality of chains of transistors102 (such as for example pass transistors) configured to selectivelycouple any of n inputs labeled as d0 through d7 to output buffer 104. Inembodiments, crossbar structure 100 may include a plurality of outputbuffers each coupled to the same or different inputs. Though only oneoutput buffer is shown in FIG. 1, embodiments are not so limited andcrossbar structure 100 is depicted with only one output buffer for easeof illustration. A plurality of control signal elements labeled as S1,S0 and C0 through C3 may be configured to selectively control one ormore transistors in the plurality of chains of transistors. For example,when control signal S0 and C1 are set to an enable voltage—and all othercontrol signals set to a disable voltage—input d3 may be selectivelycoupled to output wire 106. All other inputs may then be—in thisexample—decoupled from output wire 106. In embodiments, only a singleinput may be selectively coupled to output buffer 104 at any one time.All other inputs may be either decoupled from any output or coupled tosome other output buffer.

In embodiments, crossbar structure 100 may be part of a reconfigurablecircuit having a plurality of crossbar structures. In such areconfigurable circuit according to embodiments, at least one of thecrossbar structures may be the same as or similar to crossbar structure100. Control signal elements may be, in embodiments, a memory cellpre-configured to hold a voltage corresponding to either a logic “1” ora logic “0” depending on the desired cross-coupling. Such programming ofthe memory cells may occur when reconfigurable circuit 100 is configuredor reconfigured.

Crossbar structure 100 may also include circuit A which may include anadditional chain of transistors 110. Each transistor in additional chainof transistors 110 may be coupled to one of control signal elementsC0-C3. When any of control signal elements C0-C3 are set to an enablevoltage—in this example a logic “1”—a corresponding transistor inadditional chain of transistors 110 may be disabled. Thus, when crossbarstructure 100 is programmed to selectively couple one of n inputs tooutput buffer 104, additional chain of transistors 110 may be disabled.

If all of control signal elements C0-C3 are set to disable voltages,then each transistor of additional chain of transistors 110 may beconfigured to be enabled. In such a case, voltage source Vdd may becoupled to output wire 106 and output 104. That is, when crossbarstructure 100 is configured to disable all of n inputs to output buffer104, a constant voltage Vdd may be coupled to output buffer 104.Advantageously, all inputs may be disabled from internal capacitances ofcrossbar structure 100. Also, a constant output voltage may be coupledto output buffer 104 which may allow a constant input into a logicfunctionality circuit—either fixed or reconfigurable—such as may beincluded in a reconfigurable circuit that crossbar structure 100 may beincluded within. In embodiments, each transistor in additional chain oftransistors 110 may be a p-type metal-oxide-semiconductor field effecttransistor (pmos transistor). In alternative embodiments, each may besome other type of transistor. In such embodiments, additional logicelements may be included to allow for proper logic functionality.

Embodiments may utilize high-threshold transistors in configuration bitcircuits and/or in the additional chain of transistors to reduce leakagecurrent. In embodiments, a supply voltage may be Vdd+V_(threshold) foruse in the control signal elements so that the pluralities of chains ofpass transistors may be driven to Vdd+V_(threshold) in order to avoid avoltage threshold drop through the chains of transistors. Inembodiments, a control signal may be utilized to force all outputbuffers in a reconfigurable circuit having crossbar structures accordingto embodiments to a known state on power-on to avoid power consumptionin case a random power-on configuration of control signal elementsresults in short-circuits of output buffers at power-up.

FIG. 2 illustrates a crossbar structure having a mechanism forgenerating a constant ground-level voltage according to embodiments.Crossbar structure 200 may include circuit A which may include anadditional chain of transistors 210 coupled to corresponding ones ofcontrol signal elements C0 through C3 through inverting outputs ofcontrol signal elements C0 through C3. Similar to circuit A of FIG. 1,additional chain of transistors 210 may be configured to be disabledwhen any one of control signal elements C0 through C3 is set to anenable voltage for selectively coupling one of n inputs to output buffer204. Unlike circuit A of FIG. 1, however, when none of control signalelements C0 through C3 are set to an enable voltage, each transistor ofadditional chain of transistors may be enabled, thereby selectivelycoupling constant voltage GND (i.e. a ground-level voltage) to outputbuffer 204 via wire 206. In embodiments, additional chain of transistors210 may comprise n-type metal-oxide-semiconductor field effecttransistors (nmos transistors). This may, in embodiments, allow suchtransistors to be enabled by the logical inverse of a disabling controlsignal element voltage and couple a ground-level voltage to wire 206. Inembodiments, the remainder of crossbar structure 200 may be configuredthe same or similarly to crossbar structure 100 of FIG. 1. In this way,crossbar structure 200 may be configured to provide a constantground-level voltage (e.g. a logic “0”) as input to a logicalfunctionality module of a reconfigurable circuit element when none of ninputs is selectively coupled to output buffer 204.

Embodiments may have any number of C control signal elements and acorresponding number of either pmos or nmos transistors in theadditional chain of transistors 110 and/or 210. If N inputs are desired,then there may be needed at least k C control signals and N/k S controlsignals. Circuit delay may not be much affected by the value of kbecause the size of the pass transistors may not be much affected andeach chain of transistors may include only two transistors. Also, thecontrol signal element voltage values may remain constant duringcrossbar operation. In such embodiments, increasing the number oftransistors in the additional chain of transistors may not affect thedelay or speed of the circuit. In embodiments, increasing k may causethe unselected inputs to be connected to a small internal capacitance.Also, while for large N, increasing k may decrease the numbers ofconfiguration bits required, increasing k may increase the number of“vertical” traces required in the crossbar structures, as depicted inFIGS. 1 and 2. In embodiments, k may be chosen based on layoutconstraints and tradeoffs to minimize costs.

In embodiments not depicted in FIGS. 1 and 2, the order of transistorsin the chains of transistors selectively coupling the n inputs to theoutputs may be arranged or situated in a different order. That is, thetransistors coupled to control signal elements S may be between theoutput buffer and the transistors coupled to control signal elements Cwhich is the opposite of the order depicted in FIGS. 1 and 2.Performance may be affected by the order selected, and it may beadvantageous in embodiments to use one order or another.

FIG. 3 illustrates a crossbar structure having a mechanism to generateconstant outputs and with an additional pass transistor used to selectbetween groups of inputs in accordance with various embodiments. Inaddition to control signal elements S and control signal elements C,embodiments may include a control signal element O. Control signalelements S and control signal elements C may have the same or similarfunction as depicted and described with reference to FIGS. 1 and 2,except that, in embodiments, setting exactly one of control signalelements C and exactly one of control signal elements S may enable twodifferent transistor chains, thereby coupling both to one of internalwires 306 or 308. Control signal element O—which may also in embodimentsbe implemented as a memory cell programmed when crossbar structure 300is configured—may be coupled to one of two nmos transistors 320 and 322.Control signal element O may be coupled to nmos transistor 320 via aninverse output. Thus, only one nmos transistors 320 or 322 may beenabled at any one time to couple only one of wires 306 or 308 to outputbuffer 304. As such crossbar structure 300 may be configured to usecontrol signal elements S, C, and O to selectively couple only one of ninputs to output buffer 304.

When all of control signal elements C are set to a disable voltage,additional chain of transistors 310 may be enabled to couple constantvoltage Vdd to wire 306 and to output buffer 304. In embodiments,additional chain of transistors 310 may be coupled to only wire 306, andnot wire 308.

In embodiments, there may be more than two internal wires 306 and 308.If j is the number of desired internal common wires, then j O controlsignal elements may be required to selectively couple one of the jinternal wires to output buffer 304. In embodiments, a decoder may beused to perform the selectively coupling; in such embodiments onlylog(j) O control signal elements may be required to perform theselective coupling. j may be selected to optimize cost and/or delayamong other factors.

FIG. 4 illustrates a crossbar structure having a mechanism to generateconstant outputs and with a structure to make a subset of inputs operatefaster in accordance with various embodiments. Alternative embodimentsmay include a structure to make a subset of inputs operate faster butwithout a mechanism to generate constant outputs. Crossbar structure 400may include additional pass transistor 430 situated between a firstplurality of chains of transistors d0 through d3 and a second pluralityof chains of transistors d4 through d7. Additional pass transistor 430may be coupled to control signal element i0 to selectively couple eitherthe first plurality of chains of transistors or the second plurality ofchains transistors to output wire 406. In embodiments, if control signalelements S and C are set to enable the first plurality of chains oftransistors to couple one of inputs d4 through d7 to output buffer 404,then control signal element i0 may be set to a disable voltage toisolate the second plurality of chains of transistors. In embodiments,isolating the first plurality of chains of transistors from the secondplurality of chains of transistors whenever one of inputs d4 through d7is selectively coupled to output buffer 404 may reduce the delay ofcrossbar structure 400 between any of inputs d4 through d7 bysignificantly reducing the capacitive load on internal wire 406. Inother words, isolating the second plurality of chains of transistorsfrom wire 406 may reduce the capacitive load on internal wire 406.

If crossbar structure 400 is configured to enable any of the secondplurality of chains of transistors to selectively couple any of inputsd0 through d3 to output buffer 404, then control signal element i0 maybe set to an enable voltage to enable additional pass transistor 430 andto couple internal wire 408 to internal wire 406. In embodiments,crossbar structure 400 may be configured to operate the same as, orsimilarly to, crossbar structure 100 of FIG. 1 except that additionalpass transistor 430 may cause additional delay and capacitance to beincurred when it is enabled. Thus, crossbar structure 400 may beconfigured to provide lower delay when any of inputs d4 through d7 areselectively coupled to output buffer 406 but slower delay when any ofinputs d0 through d3 are selectively coupled to output buffer 406.

In embodiments, crossbar structure 400 may be included in areconfigurable circuit. In such embodiments, faster paths may beselected to implement critical signals in the reconfigurable circuitthat determine overall device performance. Non-critical paths may beselected for non-critical signals. In such embodiments, the overallperformance of the reconfigurable circuit may be improved overembodiments that do not provide for such division of fast inputs fromslow inputs.

In embodiments, control signal i0 may be derived directly from controlsignals S0 and S1. In such embodiments, the bit stream required toprogram crossbar structure 400 may not, and need not, include additionalbits to program control signal element i0. In alternative embodiments,additional pass transistor 430 may be placed at any point to couplefewer or more of inputs d0 through d7 to internal wire 406. Inembodiments, more or fewer inputs may be provided; eight are shown inFIG. 4—and in other figures—for illustrative purposes only.

In embodiments, more additional pass transistors (not shown) similar toadditional pass transistor 430 may be included to further divide inputsd0 through d7 into even more isolated segments. In such embodiments, thefurther away an input is from output buffer 404, the higher the delaymay be for such an input. The delay from input to output may generallyincrease with the number of series transistors. There may therefore be apractical limit to the number of pluralities of chains of passtransistors that can be separated this way.

FIG. 5 illustrates a crossbar structure to minimize the skew betweeninputs and the output in accordance with various embodiments. Reducingskew may require maintaining a constant capacitive load no matter whichof n inputs is selectively coupled to output buffer 506. In embodiments,crossbar structure 500 may include a plurality of output buffersconnected to the n inputs. Though only one output buffer is shown inFIG. 5, embodiments are not so limited. Crossbar structure 500 mayinclude two sections. The first section may be a k−1 multiplexer thatmay be implemented using transmission gates. The second section may be asecond multiplexer having tri-state inverters. An additional chain oftransistors 510 may be included within crossbar structure 500 toselectively couple constant voltage VDD to output buffer 506 when noneof n inputs are selectively coupled to output buffer 506.

Although certain embodiments have been illustrated and described hereinfor purposes of description of the preferred embodiment and otherembodiments, it will be appreciated by those of ordinary skill in theart that a wide variety of alternate and/or equivalent embodiments orimplementations calculated to achieve the same purposes may besubstituted for the embodiments shown and described without departingfrom the scope of the disclosure. Those with skill in the art willreadily appreciate that embodiments of the disclosure may be implementedin a very wide variety of ways. This application is intended to coverany adaptations or variations of the embodiments discussed herein.Therefore, it is manifestly intended that embodiments of the disclosurebe limited only by the claims and the equivalents thereof.

1. A crossbar structure comprising: n inputs and an output, where n isan integer; a plurality of chains of transistors coupled to the n inputsand to the output; a plurality of control signal elements, each coupledto one or more transistors of the plurality of chains of transistors toselectively couple said n inputs to the output; and an additional chainof transistors coupled to at least some of the plurality of controlsignal elements and to the output to selectively couple a constantoutput voltage to the output.
 2. The crossbar structure of claim 1wherein the additional chain of transistors is configured to be coupledto a voltage source.
 3. The crossbar structure of claim 1 wherein theadditional chain of transistors is configured to selectively couple theconstant output voltage to the output when the plurality of controlsignal elements are set to decouple all inputs from the output.
 4. Thecrossbar structure of claim 1 wherein each of the plurality of chains oftransistors is constituted with pass transistors, and the additionalchain is constituted with other transistors.
 5. The crossbar structureof claim 4 wherein the plurality of chains of pass transistors eachincludes at least a first pass transistor and a second pass transistor,wherein the plurality of control signal elements comprise a set offirst-order control signal elements coupled to each of the first passtransistors and a set of second-order control signal elements eachcoupled to at least one of the second pass transistors.
 6. The crossbarstructure of claim 5 wherein the plurality of control signal elementsare each coupled to less than all of the chains of transistors.
 7. Thecrossbar structure of claim 5 further comprising a set of additionalpass transistors each coupled between the output and different ones ofthe second pass transistors, wherein the plurality of control elementsfurther comprises a third-order control element coupled to theadditional pass transistors, and wherein the set of second-order controlsignal elements are each coupled to more than one of the second passtransistors.
 8. The crossbar structure of claim 5 further comprising anoutput wire coupled between each of the chains of pass transistors andthe output, and an isolation transistor coupled to the output wire toisolate a first subset of the plurality of pass transistors from asecond plurality of the pass transistors when the isolation transistoris disabled by another control signal.
 9. The crossbar structure ofclaim 5 further comprising a common output wire coupled to the outputand a tri-state inverter coupled to the output wire and to subset of theplurality of pass transistors to selectively couple the subset of theplurality of pass transistors to the output wire.
 10. The crossbarstructure of claim 1 wherein the plurality of control signal elementseach comprise a memory cell.
 11. A reconfigurable circuit comprising: aplurality of crossbar devices coupled to one another, at least one ofthe crossbar devices having: n inputs and an output, where n is aninteger; a plurality of chains of transistors coupled to the n inputsand to the output; a plurality of control signal elements, each coupledto one or more transistors of the plurality of chains of transistors toselectively couple said n inputs to the output; and an additional chainof transistors coupled to at least some of the plurality of controlsignal elements and the output to selectively couple a constant outputvoltage to the output.
 12. The reconfigurable circuit of claim 11wherein the additional chain of transistors is configured to be coupledto a voltage source.
 13. The reconfigurable circuit of claim 11 whereinthe additional chain of transistors is configured to selectively couplethe constant output voltage to the output when the plurality of controlsignal elements are set to decouple all inputs from the output.
 14. Thereconfigurable circuit of claim 11 wherein each of the plurality ofchains of transistors is constituted with pass transistors, and theadditional chain is constituted with other transistors.
 15. Thereconfigurable circuit of claim 14 wherein the plurality of chains ofpass transistors each includes at least a first pass transistor and asecond pass transistor, wherein the plurality of control signal elementscomprise a set of first-order control signal elements coupled to each ofthe first pass transistors and a set of second-order control signalelements each coupled to at least one of the second pass transistors.16. The reconfigurable circuit of claim 15 wherein the plurality ofcontrol signal elements are each coupled to less than all of the chainsof transistors.
 17. The reconfigurable circuit of claim 15 furthercomprising a set of additional pass transistors each coupled between theoutput and different ones of the second pass transistors, wherein theplurality of control elements further comprises a third-order controlelement coupled to the additional pass transistors, and wherein the setof second-order control signal elements are each coupled to more thanone of the second pass transistors.
 18. The reconfigurable circuit ofclaim 15 further comprising an output wire coupled between each of thechains of pass transistors and the output, and an isolation transistorcoupled to the output wire to isolate a first subset of the plurality ofpass transistors from a second plurality of the pass transistors whenthe isolation transistor is disabled by another control signal.
 19. Thereconfigurable circuit of claim 11 wherein the constant output voltageis either Vdd or ground.
 20. The reconfigurable circuit of claim 11wherein the plurality of control signal elements each comprise a memorycell. 21-26. (canceled)